1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device comprising a printed circuit board ball grid array (BGA) and a package for the semiconductor device and, more particularly, to a method for manufacturing a semiconductor device comprising a printed circuit board BGA package in which a plurality of printed wiring boards are laminated, and a package for the semiconductor device.
2. Description of the Background Art
FIG. 57 is a sectional view showing the structure of a semiconductor device according to the prior art. In FIG. 57, reference numeral 1 designates a semiconductor device comprising a printed circuit board BGA package, reference numeral 2 designates a chip in the semiconductor device 1, reference numeral 3 designates a slug on which the chip 2 is placed, reference numeral 4 designates a die bonding resin bonding the chip 2 to the slug 3, reference numeral 5 designates a frame around the chip 2 and having a first main surface to which the slug 3 is bonded, reference numeral 6 designates an adhesive bonding the frame 5 to the slug 3, reference numeral 7 designates a solder ball on a second main surface of the frame 5, reference numeral 8 designates a wire electrically connecting the chip 2 to the frame 5, reference numeral 9 designates a cavity in the central portion of the frame 5 housing the chip 2, reference numeral 10 designates a sealing resin filling the cavity 9 and sealing the chip 2, and reference numeral 11 designates a dam on the second main surface of the frame 5, closing an opening and preventing the sealing resin 10 from flowing out.
The frame 5 comprises two laminated double-sided printed circuit boards 15 and 16 and a prepreg 17 bonding them. The double-sided printed circuit board 15 has wiring layers 19 and 20 on both sides of an insulating substrate 18. The double-sided printed circuit board 16 has wiring layers 22 and 23 on both sides of an insulating substrate 21.
The wiring layers 19 and 20 and the wiring layers 22 and 23 on both sides of the double-sided printed circuit boards 15 and 16 are connected by interstitial via holes. The double-sided printed circuit boards 15 and 16 are connected by a through hole 24. The signals and power are exchanged between the chip 2 and a board on which the semiconductor device 1 is placed through the wire 8, the wiring layers 19, 20, 22, and 23, the through hole 24, the interstitial via hole 25, the solder ball 7, and the like.
A method for manufacturing the printed circuit board BGA package shown in FIG. 57 is described with reference to FIGS. 43 to 57.
First, a double-sided printed circuit board 15 having copper foils 30 and 31 laminated on both sides is prepared (see FIG. 43).
Then a hole 32 for an interstitial via hole, penetrating the double-sided printed circuit board 15, is formed (see FIG. 44). The double-sided printed circuit board 15 is plated with a copper plated layer 33. Thus, an interstitial via hole 25 is formed (see FIG. 45). As shown in FIG. 46, the interstitial via hole 25 is filled with a resin 34. Consequently, no gap which penetrates the double-sided printed circuit board 15 is present. A wiring layer 20 of the double-sided printed circuit board 15 is then patterned (see FIG. 47).
After performing the same steps as shown in FIGS. 43 to 47, a double-sided printed circuit board 16 is prepared. The circuit board 15 includes the interstitial via hole 25 filled with the resin 34 and a patterned wiring layer 22 (see FIG. 48). The double-sided printed circuit board 16 comprises copper foils 35 and 36 and a copper plated layer 37 thereon.
The double-sided printed circuit board 15 shown in FIG. 47 and the double-sided printed circuit board 16 shown in FIG. 48 are bonded together by a prepreg 17. Consequently, the laminated printed circuit board 38 is an aggregate of the double-sided printed circuit boards 15 and 16 (see FIG. 49). A chamber 39 for forming a cavity 9 shown in FIG. 57 is located between the double-sided printed circuit boards 15 and 16 in the central portion of the laminated printed circuit board 38. A hole 40 penetrating the laminated printed circuit board 38 is located in a region 41 of the laminated printed circuit board 38 where the prepreg 17 is inserted (see FIG. 50). The laminated printed circuit board 38 is plated with a copper plated layer 42. Thus, a through hole 24 is formed (see FIG. 51). The laminated printed circuit board 38 is immersed in a plating solution to be plated with copper. However, the interstitial via hole 25 has been filled with a resin so that the chamber 39 has been sealed so the plating solution does not invade the chamber 39.
Subsequently, the through hole 24 is filled with a resin 43 as shown in FIG. 52. Then a wiring layer 19 is patterned (see FIG. 53). At the same time, the copper foil 30 and the copper plated layers 33 and 42 of the wiring layer 19, located in an upper region 44 of the chamber 39, are removed. An insulating substrate 18 in the upper region 44 is machined with a router to form an opening 45. After that, a nickel-gold layer 46 is plated on the copper plated layers 37 and 42 (see FIG. 54).
As shown in FIG. 55, a wiring layer 23 is patterned. At the same time, the copper foil 35 and the copper plated layers 37 and 42 in a lower region 47 of the chamber 39 are removed. As shown in FIG. 56, an opening 48 is formed in the lower region 47 so that a frame 5 is completed. A slug 3 is bonded to the frame 5 with an adhesive 6.
The chip 2 is bonded to the slug 3 with a die bonding resin 4 and the chip 2 is connected to the nickel-gold plated layer 46 by a wire 8. After a dam 11 is put in place, the cavity 9 is filled with a sealing resin 10. Then, a solder ball 7 is formed on the nickel-gold plated layer 46 of the wiring layer 19. The printed circuit board BGA package is thus completed (see FIG. 57).
In the semiconductor device and the method for manufacturing the semiconductor device according to the prior art, the copper plated layers 33 and 37 are formed on the copper foils 31 and 36 of the wiring layers 20 and 22, and the copper plated layer 33 or 37 and the copper plated layer 42 are formed doubly on the copper foils 30 and 37 of the wiring layers 19 and 23. Consequently, the thicknesses of the wiring layers 19, 20, 22, and 23 are increased. For this reason, it is hard to reduce the pitches of patterns on the wiring layers 19, 20, 22, and 23.
This problem will be described with reference to FIGS. 58 and 59. FIG. 58 is a sectional view showing a wiring layer 50A including a copper foil 52 and a copper plated layer 51 with a pattern having a minimum pitch. The formed pattern has a predetermined inclination 53 which depends on the conditions of patterning. In FIG. 58, reference numeral 55 designates a minimum required space between patterns, and reference numeral 54 designates pattern pitch. FIG. 59 is a sectional view showing a wiring layer 50B including only the copper foil 52 and a pattern at the minimum pitch. Similar to the section of the pattern shown in FIG. 58, the pattern shown in FIG. 59 has a predetermined inclination 53 which depends on the conditions of patterning. In FIG. 59, reference numeral 55 designates a minimum required space between patterns, and reference numeral 56 designates pattern pitch. As seen from a comparison of FIGS. 58 and 59, the pitch 54 is greater than the pitch 56. When the thickness of the wiring layer increases, it becomes harder to reduce the pitch of the wiring pattern.
Furthermore, the through hole 24 and the interstitial via hole 25 should be plated in separate plating steps. Consequently, the number of manufacturing steps is increased. In addition, it is necessary to immerse the laminated printed circuit board 38 in a plating solution when forming the through hole 24. For this reason, filling the interstitial via hole 25 with the resin cannot be omitted.